The present invention relates to verification of electronic hardware designs. More specifically, the present invention utilizes a logic simulator with a hardware model in combination with an instruction set simulator to create a hardware-software co-verification environment.
The use of computer simulation has become widespread in many areas such as circuit design. The cost of manufacturing an integrated circuit is extremely high, and it is desirable that the hardware incorporated into the integrated circuit be tested prior to actual fabrication of the chip. Therefore, integrated circuit manufacturers often use simulators to test the hardware and the software intended to be executed by the hardware.
In performing design verification, it is frequently necessary to simulate not only the newly designed hardware, but also enough of the surrounding electronic environment to provide suitable interface signals to the circuit under test. For this purpose, the engineer creates or obtains a model of a xe2x80x9cmasterxe2x80x9d device that can, by way of instructions, manipulate the simulation environment in a desired fashion and produce deterministic results. For example, in order to test a memory chip, an engineer requires a master model to generate functionally and correctly read and write control signals to the chip within the simulation environment Therefore, the constraints imposed by the instruction set of the master model limit the extent of verification.
A very popular series of microcontrollers have emerged for serial interfaces in the digital communications arena. For example, first in the family was the Motorola 68302 micro-controller. It was replaced over time in terms of the popularity of the Motorola 68360 micro-controller. Then, the Motorola Power PC and MPC860 micro-controller followed. The latest version of the microcontroller is the Motorola MPC8260. Each micro-controller is characterized by a very popular microprocessor core, and contains a series of serial peripherals that are controlled by a common serial communications engine. As a consequence, the micro-controller provides tools to support software development associated with systems that use these particular kinds of chips. A hardware model has been built to match each micro-controller to model portions of the design hardware.
However, a hardware model is not an efficient means by which to develop software. The processor in the hardware model is often a dynamic device that must maintain a running clock in order to retain data. Because the hardware model simulates the system responses event by event for an arbitrarily small time slice, the microprocessor must wait for each simulation cycle to be completed by the hardware simulator. Therefore, the microprocessor must be reset at the start of each simulation cycle, and all the previous vectors rerun. As the simulations gets longer, the time taken to rerun all the previous vectors increases. Executing the software takes a large number of clock cycles, often exceeding the maximum amount of vector memory available for the hardware model, and thus severely limiting the length of the software. In addition to the large memory requirement in the hardware model, the execution of the software at the object code level does not provide a convenient means for debugging the program.
Further, it is not feasible to use a prototype of the hardware design with an evaluation board because that will not allow the customer to do an arbitrary design. Instead, typically the customer""s design is based around one of these micro-controllers because the design requires the peripherals of the micro-controller to access the design. The micro-controller has an interface to memory which forms the basis for executing instructions to the serial interface and provides the communications to the hardware design.
Creating a hardware model in a simulator context is previously known. The Synopsys Eaglei@ family utilizes instruction set simulators, bus functional models and other traditional hardware-software co-verification tools for a microprocessor. Synopsys Eaglei @ is a trademark of Synopsys, Inc. of Mountain View, Calif. While the use of a hardware model can provide a full functional processor model, the significant cost of the hardware model is not always reflected by an increase in simulation performance. The hardware model contains a vector memory to store the input data for each pin of the microprocessor for each time slice of the hardware simulator. A time slice can be arbitrarily small, and is typically less than a typical microprocessor clock cycle. The detection of timing problems requires an event by event analysis, including propagation delays of the hardware design. The hardware model runs lockstep with the hardware simulator with the microprocessor generating the next set up binary signals from the vector memory at the microprocessor pin connections for incorporating with the next simulated step of the hardware simulator. Thus, the hardware model operates in complete synchronization with the hardware simulator.
The current problem facing the user is that the standard instruction set simulator tools addressing the processor would not properly address the communication between the peripheral and the design to be tested. Additionally, it is very difficult to make a software model of the entire microcontroller because the modes associated with the multiple peripherals and the different ways they can be configured does not lend itself to modeling very efficiently. It might take years to build a completely accurate softvare model to accomplish such a task, whereas a hardware model for a microcontroller can be built in much less time, and is intrinsically accurate.
The present invention in its preferred embodiment represents the ability to model hardware designs that include a microcontroller integrated circuit which has a processor and peripheral devices through the combination of hardware model, instruction set simulator (ISS), and logic simulator within a hardware-software co-verification environment. The present invention accomplishes this goal by breaking the processor away from the peripheral devices, and substituting an ISS so that it can run software with much higher performance. Furthermore, when the peripheral devices"" accuracy is an important requirement of the simulation, they can be modeled with perfect accuracy by the hardware model.
In accordance with one aspect of the present invention, the method and apparatus for modeling using this hardware-software co-verification environment comprises a logic simulator program simulating the hardware design, and an ISS for representing the operation of the processor. The logic simulation contains a bus functional model (BFM), a hardware model of an integrated circuit, a remaining hardware design, and an initialization memory block. According to the preferred embodiment, the integrated circuit is a micro-controller.
When the processor of the hardware modeled microcontroller is disabled, the ISS is coupled to the logic simulation in its place. The object is to provide the high speed and internal visibility of the ISS, with the accuracy and easier availability of the rest of the micro-controller modeled in the hardware model. The design process is greatly simplified by not having to generate a software model of the peripheral devices. Additionally, the modeling accuracy is perfect because the actual peripheral devices of the integrated circuit in the hardware model are used.
When the software instruction stream executed by the ISS would cause a bus cycle to be issued by the actual processor, such as for a read or write of external memory or a peripheral devices"" register, the ISS send a signal to the BFM, which issues the bus cycle to the rest of the design which is in simulation, including the hardware model. The BFM translates the bus cycle from the command issued by the ISS to the level of pin changes happening in multiple time steps in simulation, as if the actual processor was present.
In accordance with another aspect of the present invention, the processor part of the hardware modeled microcontroller is disabled, even if there is no facility built into the microcontroller integrated circuit to literally turn off. Methods and apparatus of this invention cause the processor part to be effectively disabled, so far as the ISS and the logic simulator are functioning, even if not literally turned off, while retaining complete accuracy.
In accordance with another aspect of the present invention, the ISS is uncoupled from time synchronization with the rest of the design in logic simulation, for example, during periods of little interaction between instruction execution and the peripheral devices of the other hardware, such as while the operating system is initialized. Much faster verification performance results. Furthermore, the instruction stream executed in the ISS may issue bus cycles which access registers in the peripheral devices or the rest of the design while the ISS is uncoupled from logic simulation. The hardware-software co-verification environment of this invention detects such occurrences and temporarily couples the ISS with the logic simulator to correctly execute such bus cycles.
In accordance with another aspect of the present invention, any of the hardware modeled peripheral devices may issue an interrupt request to the processor, which is intercepted by the BFM and passed on to the ISS for servicing, as if the actual processor was present in the logic simulation. Likewise, any of the hardware modeled peripheral devices may issue a direct memory access (DMA) bus cycle, which is intercepted by the BFM and passed on to the rest of the design (ROD) in logic simulation.
The nature, principle and utility of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.